(a) Field of the Invention
The present invention relates to a method for fabricating a multi-level mask ROM (read only memory) and, more particularly, to a method for fabricating a mask ROM having a multi-level ROM cell.
(b) Description of the Related Art
A conventional nonvolatile semiconductor memory device having an insulated gate field effect transistor (IGFET), such as MOSFET, in each memory cell generally stores a 1-bit data, namely "1" or "0". With the demand for increasing the storage capacity in the nonvolatile semiconductor memory device, a multi-level nonvolatile semiconductor memory device is proposed recently which includes a plurality of multi-level memory cells each storing multi-level data, such as 2-bit data.
A method for fabricating a mask ROM, a typical nonvolatile semiconductor memory device, having a multi-level (or 2-bit) memory cell is described in JP-A-7-142611, for example. FIGS. 1A to 1D consecutively show the fabrication process described in the publication, wherein memory cell transistors B1 to B4 have different thresholds Vb1 to Vb4 such that Vb1&lt;Vb2&lt;Vb3&lt;Vb4.
All the memory cell transistors B1 to B4 have a common basic structure including a gate insulating film 102 formed on a semiconductor substrate 101, a gate electrode 103 formed thereon, and source/drain diffused regions 104 in the surface region of the semiconductor substrate 101, with a channel area disposed therebetween below the gate electrode 103. An interlayer dielectric film 105 overlies the entire basic structure.
In FIG. 1A, a first resist mask 106 having first openings 107 exposing the interlayer dielectric film 105 at the memory cell transistors B2 and B4 is formed on the interlayer dielectric film 105 by a photolithographic technique. A first ion-implantation using boron ions is conducted through the first openings 107 and the gate electrode 103 to form first injected regions 108 at the channel areas of the memory cell transistors B2 and B4. The first ion implantation assures the threshold Vb2 for the memory cell transistor B2, by employing a specified dosage with an acceleration energy of about 250 keV.
Subsequently, as shown in FIG. 1B, portions of the interlayer dielectric film 105 overlying the memory cell transistors B2 and B4 are selectively etched using the first photoresist mask 106 as an etching mask to reduce the thickness of the portions of the interlayer dielectric film 105, followed by removal of the first photoresist mask 106.
Thereafter, as shown in FIG. 1C, a second photoresist mask 106a is formed having openings 109 for exposing memory cell transistors B3 and B4, followed by a second ion-implantation through the openings 109 and the gate electrodes 103 to form injected regions 110 in the channel areas of the memory cell transistors 13 and B4. In this step, the reduced thickness of the interlayer dielectric film 105 in the memory cell transistor B4 provides a larger depth for the injected region 110 in the memory cell transistor B4 than the channel area in the memory cell transistor B4. The second ion-implantation assures the threshold. Vb3 for the memory cell transistor B3 by employing a specified dosage of the boron ions.
Thereafter, a third ion-implantation is conducted using the is second photoresist mask 106a as it is to form injected regions 112 in the channel area of the memory cell transistor. B4. In this step, an injected region 111 is formed in the gate electrode 103 of the memory cell transistor B3 due to a larger thickness of the interlayer dielectric film 105 than the thickness of the interlayer dielectric film 105 in the memory cell transistor M. Thus, the third ion-implantation does not affect the threshold Vb3 of the memory cell transistor B3 while assuring the, threshold Vb4 of the memory cell transistor B4, which is determined by the second ion-implantation and the third ion-implantation.
In the conventional fabrication method for the multi-level mask ROM as described above, the ion-implantation for specifying the multi-level data in the memory cell transistors (referred to as "code ion-implantation", hereinafter) has a disadvantage in that the injected region formed by the code ion-implantation has a significant extension in the transverse direction with respect to the direction of the ion injection, as detailed below.
FIG. 2 schematically shows an exemplified top plan view showing the openings of the mask ROM in a fabrication step thereof, wherein source/drain diffused regions N1, N2 and N3 extend perpendicularly to the extending direction of the gate electrodes G1, G2 and G3. In this configuration, the channel area of a memory cell transistor is disposed below the gate electrode, such as G1, between the source/drain regions, such as N1 and N2. The code ion-implantation is conducted through the openings K1, K2 and K3 formed in a photoresist mask.
In the ion-implantation, the injected ions are scattered by the surface of the interlayer dielectric film or the gate electrode, especially by the diagonal surface 113 of the interlayer dielectric film 105, when the injected ions pass through the interlayer dielectric film or the gate electrode.
The scattering is one of the factors preventing a higher integration for the memory cell transistors of the multi-level mask ROM because the transverse extension of the injected region in a memory cell transistor affects the threshold of the adjacent memory cell transistors.